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| U62H64 Automotive Fast 8K x 8 SRAM Features ! Fast 8192 x 8 bit static CMOS ! ! ! ! ! Description The U62H64 is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E1 and E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. ! ! ! ! ! ! ! ! ! RAM 35 ns Access Time Bidirectional data inputs and data outputs Three-state outputs Data retention mode at Vcc > 2V Data retention current at 2 V: < 3 A (K-Type) < 50 A (A-Type) Standby current < 5 A (K-Type) < 100 A (A-Type) TTL/CMOS-compatible Automatic reduction of power dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges -40 to 85 C -40 to 125 C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 200 mA Package: SOP28 (300 mil) Pin Configuration Pin Description n.c. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W (WE) E2 (CE2) A8 A9 A11 G (OE) A10 E1 (CE1) DQ7 DQ6 DQ5 DQ4 DQ3 Signal Name A0 - A12 DQ0 - DQ7 E1 E2 G W VCC VSS n.c. Signal Description Address Inputs Data In/Out Chip Enable 1 Chip Enable 2 Output Enable Write Enable Power Supply Voltage Ground not connected SOP Top View April 20, 2004 1 U62H64 Block Diagram A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 A4 A5 Row Decoder Row Address Inputs Memory Cell Array 128 Rows 64 x 8 Columns Column Address Inputs Column Decoder DQ0 Bidirectional Data I/O Sense Amplifier/ Write Control Logic DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS W G Address Change Detector Clock Generator E2 E1 Truth Table Operating Mode Standby/not selected Internal Read Read Write * H or L E1 * H L L L E2 L * H H H W * * H H L G * * H L * DQ0 - DQ7 High-Z High-Z High-Z Data Outputs Low-Z Data Inputs High-Z 2 April 20, 2004 U62H64 Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage. Absolute Maximum Ratings a Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Output Short-Circuit Current at VCC = 5 V and VO = 0 V c a Symbol VCC VI VO Min. -0.3 -0.3 -0.3 -40 -40 -65 Max. 7 VCC + 0.5 b VCC + 0.5 b 85 125 150 200 Unit V V V C C C mA K-Type A-Type Ta Tstg |IOS| b c Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Power Supply Voltage Data Retention Voltage Input Low Voltage d Input High Voltage d Symbol VCC VCC(DR) VIL VIH Conditions Min. 4.5 2.0 -0.3 2.2 Max. 5.5 Unit V V V V 0.8 VCC + 0.3 -2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns April 20, 2004 3 U62H64 Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) VCC VIL VIH tcW Conditions = 5.5 V = 0.8 V = 2.2 V = 35 ns Min. Max. Unit 50 mA Supply Current - Standby Mode (CMOS level) ICC(SB) = 5.5 V VCC VE1 = VE2 = VCC - 0.2 V K-Type A-Type = 5.5 V VCC VE1 = VE2 = 2.2 V = 2.0 V VCC(DR) VE1 = VE2 = VCC(DR) - 0.2 V K-Type A-Type VCC IOH VCC IOL VCC VOH VCC VOL VCC VIH VCC VIL VCC VOH VCC VOL = = = = = = = = 4.5 V -4.0 mA 4.5 V 8.0 mA 4.5 V 2.4 V 4.5 V 0.4 V 2.4 8.0 -2 5 100 5 (typ. 2) A A mA Supply Current - Standby Mode (TTL level) Supply Current - Data Retention Mode ICC(SB)1 ICC(DR) 3 50 0.4 -4.0 2 - A A V V mA mA A A Output High Voltage Output Low Voltage Output High Current Output Low Current Input High Leakage Current Input Low Leakage Current Output Leakage Current High at Three-State Outputs Low at Three-State Outputs VOH VOL IOH IOL IIH IIL = 5.5 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 5.5 V = 0V IOHZ IOLZ -2 2 - A A 4 April 20, 2004 U62H64 Symbol Switching Characteristics Time to Output in Low-Z from E1 LOW or E2 HIGH G LOW W HIGH Cycle Time Write Cycle Time Read Cycle Time Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip Enable to End of Write Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time Data Hold Time Address Hold from End of Write Output Hold Time from Address Change E1 HIGH or E2 LOW to Output in High-Z W LOW to Output in High-Z G HIGH to Output in High-Z E1 LOW or E2 HIGH to Power-Up E1 HIGH or E2 LOW to Power-Down Alt. tLZCE tLZOE tLZWE tWC tRC tACE tOE tAA tWP tCW tAS tCW tWP tDS tDH tAH tOH tHZCE tHZWE tHZOE tPU tPD IEC ten(E) ten(G) ten(W) tcW tcR ta(E) ta(G) ta(A) tw(W) tw(E) tsu(A) tsu(E) tsu(W) tsu(D) th(D) th(A) tv(A) tdis(E) tdis(W) tdis(G) 0 35 20 25 0 25 20 15 0 0 5 15 15 12 Min. Max. Unit 5 0 0 35 35 35 15 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Retention Mode E1-Controlled VCC VCC(DR) 2 V 2.2 V tDR 0V Data Retention trec 2.2 V E1 0V Data Retention Mode E2-Controlled VCC VCC(DR) 2 V 0.8 V tDR Data Retention trec 0.8 V E2 4.5 V 4.5 V VE2(DR) VCC(DR) - 0.2 V or V E2(DR) 0.2 V VCC(DR) - 0.2 V VE1(DR) V CC(DR) + 0.3 V VE1(DR) VCC(DR) - 0.2 V or V E1(DR) 0.2 V VE2(DR) 0.2 V Chip Deselect to Data Retention Time Operating Recovery Time at VCC(DR) April 20, 2004 5 tDR: trec: min 0 ns min t cR U62H64 Test Configuration for Functional Check 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 E1 E2 W G VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Input level according to the relevant test measurement VIH VIL ment of all 8 output pins Simultaneous measure- 481 VO 30 pF e 255 VSS e In measurement of tdis(E), tdis(W), tdis(G) , ten(E), ten(W) , ten(G) the capacitance is 5 pF. Capacitance Input Capacitance Output Capacitance Conditions VCC = 5.0 V VI = VSS f Ta = 1 MHz = 25 C Symbol CI CO Min. Max. 8 10 Unit pF pF All pins not under test must be connected with ground by capacitors. Ordering Code Example Type Package S = SOP28 (300 mil) Operating Temperature Range K = -40 to 85 C A = -40 to 125 C U62H64 S K 35 L Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Power Consumption blank = Standard (only A-Type) L = Low Power (only K-Type) Access Time 35 = 35 ns f on special request Device Marking (example) Product specification Assembly location and trace code Internal Code ZMD U62H64SK 35L C 0425 1 ZZ G1 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 6 April 20, 2004 U62H64 Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled) tcR Ai DQi Output Previous Data Valid tv(A) Addresses Valid ta(A) Output Data Valid Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled) tcR Ai E1 tsu(A) Addresses Valid ta(E) ten(E) tsu(A) ta(E) ten(E) ta(G) tdis(G) High-Z tPU* 50 % tdis(E) tdis(E) E2 G DQi Output ten(G) Output Data Valid tPD* 50 % ICC(OP) ICC(SB) * The same applies to E1 Write Cycle 1 (W-controlled) tcW Ai E1 E2 W DQi Input tdis(W) tsu(A) Addresses Valid tsu(E) th(A) tsu(E) tw(W) tsu(D) th(D) ten(W) Input Data Valid High-Z DQi Output G April 20, 2004 7 U62H64 Write Cycle 2 (E1-controlled) tcW Ai E1 E2 E2 W DQi Input tsu(A) Addresses Valid tw(E) th(A) tsu(E) tsu(W) tsu(D) ten(E) tdis(W) th(D) Input Data Valid High-Z DQi Output G Write Cycle 3 (E2-controlled) tcW Ai E1 tsu(A) Addresses Valid tsu(E) th(A) E2 W DQi Input ten(E) tw(E) tsu(W) tsu(D) tdis(W) th(D) Input Data Valid DQi Output High-Z G undefined L- or H-level The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved. 8 April 20, 2004 U62H64 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. April 20, 2004 Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de |
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